The present invention relates to designing very-large-scale integrated (VLSI) circuits, and particularly concerns methods for reducing the time skew between the arrival times of clock signals at different logic circuits within a system of digital chips in a system, and systems of chips having a reduced clock skew.
Digital systems, such as data processors, are commonly implemented as a system of multiple VLSI chips, typically three or four to a dozen or more on a printed-circuit board. Depending upon the semiconductor technology, each chip may have up to 75,000 or more logic circuits, all operating at nanosecond or picosecond gate delays. The overall operation of such a system depends upon a number of clock signals for synchronizing the logic functions over all the chips. The maximum speed of the system depends linearly upon a cycle time established by one or more of these clocks.
It is absolutely essential that such clock signals arrive in a predetermined sequence at various functional logic circuits within the system, both on the same chip and on different chips. The cycle time must be deliberately limited to ensure that skew in the arrival times does not cause errors in the logic. Skew can occur when clock signals pass through different numbers of gates on their way to different destinations. Skew can occur when the loading on different branches of a clock tree are different. Skew can occur when the wiring in different branches introduces different delays.
Clock skew causes two types of problems "Early mode" faults occur when two supposedly sequential clock signals overlap each other, resulting in the transmission of a data signal one clock cycle earlier than intended "Late mode" problems occur when there is a reduction of the usable portion of the system cycle time due to clock separation. Both types of problems can occur among the circuits of a single chip and between the circuits of two different chips in a system.
A typical processor board having half a dozen chips using conventional CMOS technology may operate at a cycle time of 50 nsec. The entire system could operate about 10% to 20% faster without changing anything except for the skew in the arrival times of the clocks at different circuits and chips in the system. Moreover, any decrease in clock skew translates into a linear decrease in the achievable cycle time: one nanosecond of skew eliminated is one nanosecond shorter cycle time.